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Events calendar 2019

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Near-Threshold Logic Benefits the Full Application Stack

NOV
14
2019
14. NOV 2019

Presentation Hall B1 SEMICON EUROPA > TechARENA 1 & 2 - Technological Platform for Innovation > Smart Design | Designing Electronic Systems for Advanced Applications

15:00-15:20 h | Hall B1 Tech Arena 1, Booth B1.175

Subjects: SEMICON EUROPA

Speaker: Lauri Koskinen (Minima Processor)

Type: Presentation

Speech: English

Minima dynamic margining enables any processor or DSP core to operate at its minimum-energy point and achieve up to 15x energy savings. As energy is quadratically proportional to voltage, the energy savings are achieved with ultra-low-voltage operation. Minima enhanced logic operates down to 0.4V while still meeting user set performance requirements. Additionally, Minima margining enables ultra-wide DVFS that allows operation from ultra-low to nominal voltage.
Dynamic margining is a HW-SW solution that is grounded on netlist-level logic enhancements. Minima IP enables the processor to modify power usage in real time in response to performance needs, process variations, or environmental conditions. The enhancements are completely compliant with mainstream CAD.
The Minima toolset includes application-level profiling that allows tuning for UW-DVFS in the whole vertical application.

Speaker,
Minima Processor

Lauri Koskinen

Lauri Koskinen

Minima Processor

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Informations

Speaker,
Minima Processor

Lauri Koskinen
Lauri Koskinen
CTO and Co-founder

Location

Eingang
Nord-West
ICM
Eingang
Nord
Eingang
West
Atrium
Eingang
Nord-Ost
Eingang
Ost
Conference
Center Nord
Freigelände
C1
C2
C3
C4
C5
C6
B0
B1
B2
B3
B4
B5
B6
A1
A2
A3
A4
A5
A6

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