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Events calendar 2019

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Innovative Interconnect and Encapsulation Developments for Wafer Level Packaging

NOV
12
2019
12. NOV 2019

Presentation Hall ICM - Internationales Congress Center München SEMICON EUROPA > Strategic Materials Conference > Session 1 - Materials and Processes for Wafer-Level Packaging

13:40-14:05 h | ICM - Internationales Congress Center München ICM Room 13a, 1st Floor

Subjects: SEMICON EUROPA

Type: Presentation

Speech: English

Smart Electronics’ trends like Big Data, Artificial Intelligence, Autonomous Driving and 5G continue to drive advanced semiconductor innovation towards higher functionality with smaller form factors and reduced power consumption. To meet these future demands, semiconductor package designs continue to evolve towards WAFER scale assembly using 3D Stacking and System-in-Package (SiP) type of architectures. Through Silicon Via (TSV) is enabling 3D die stacking for High Bandwidth Memory (HBM) allowing for finer pitch. Wafer Level Packaging (WLP) for both Fan-In and Fan-Out are also gaining momentum rapidly and same for Panel Level Packaging (PLP) showing significant progress. With this move towards SiP, increasing data demands, faster processing speeds and the emergence of 5G, traditional wafer fabrication companies are getting more in the driver's seat of Semiconductor Packaging.New finer pitch interconnect and low warpage encapsulation developments are essential for such high-density and challenging 2.5/3D device manufacturing processes, stress management for larger devices and increasing long-term reliability requirements. Next to this, increasing heat generation and dissipation, Fan-In and Fan-Out process compatibility (adhesion, die shift) and further need for miniaturization (Keep-out-Zone) are key challenges for Semiconductor Packaging material suppliers. < div >This presentation will give a technical overview of the advanced wafer level packaging material developments to enable next gen 2.5D and 3D chip designs :< div >- “Wafer Applied Underfill Films” for 3D Stacking of thin TSV wafers with increasing thermal performance and faster processing- Low shrinkage and ultra-low warpage wafer encapsulants and coatings for Fan-In and Fan-Out applicationsThese developments are aimed to meet the market's sustainability, miniaturization and high reliability requirements with providing reliable, scalable and environmental-friendly adhesive and encapsulation solutions.

Informations

Ruud de Wit

Ruud de Wit is responsible for managing Henkel's Semiconductor Packaging Materials business development within EIMEA region. Ruud has a BSc degree in Mechanical Engineering followed by several polymer, sales and marketing courses. Ruud is working for Henkel since 1990 in multiple positions including technical customer service, quality assurance and engineering, and global semiconductor account and product management.

Ruud de Wit
EIMEA SU Head Semiconductors

Location

Eingang
Nord-West
ICM
Eingang
Nord
Eingang
West
Atrium
Eingang
Nord-Ost
Eingang
Ost
Conference
Center Nord
Freigelände
C1
C2
C3
C4
C5
C6
B0
B1
B2
B3
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B6
A1
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A6

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