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Innovative Panel Plating for finer line spacing and better uniformity to allow semiconductor or embedded die assembly for Heterogeneous Integration

NOV
13
2019
13. NOV 2019

Presentation Hall ICM - Internationales Congress Center München SEMICON EUROPA > Advanced Packaging Conference > Session 5: Advanced Packaging

11:55-12:20 h | ICM - Internationales Congress Center München ICM Room 13b, 1st Floor

Subjects: SEMICON EUROPA

Chairman: Thomas Oppert (, PacTech - Packaging Technologies GmbH)

Type: Presentation

Speech: English

Panel Plating requirements are much more demanding as more applications migrate from Silicon to Panel assembly such as Panel level Fan Out to leverage the large sizes of the Panels. More recently Heterogeneous Integration like Intel’s Embedded Bridge (EMIB) or various other embedded die concepts are also pushing the boundary for typical panel structures. Line widths and spaces less than 10 Microns, thickness uniformity better than 10%, via topology free of voids and the same height as the redistribution lines are critical. Traditional Panel Plating Tools are mostly for bulk processing and are not designed to handle these additional requirements so a new tool was required to overcome these challenges. An Electroplating process is used with a Single panel per reservoir approach. An overhead transporter will bring the individual panels that will have been pre inserted in a rigid panel holder designed to handle large currents as well as reduce the warpage to a series of plating reservoirs as well as pre and post processing steps with the tool . The first process is to reduce voiding by removing all air in a vacuum chamber and then inserting degassed water in the same chamber to “prewet’ the panel. The Plating cells are customized for each metal layer but include a mechanism to allow the panel to be lowered in a structure with a shield to better align the electrical current between the material anodes and the Panel Holder as well as a louvered shear plate that is activated at a certain frequency to improve the seed layering. This whole mechanism needs to be very close to the panel and minimize any warping.This presentation will demonstrate that it is possible to achieve better line density, bump thickness uniformity and void free vias to allow semiconductor like assembly for Heterogeneous Integration on a standard Printed Circuit Board instead of more expensive semi additive processes or silicon interposers

Informations

Richard Boulanger

Richard Boulanger graduated as an Industrial Engineer from Ecole Polytechnique of the University of Montreal. He worked for IBM in Canada and in the United States for Semiconducotr Assembly and Ceramic Processing. He held several positions including Site Quality manager, Memory Business Unit manager and Director of Strategy.He then worked for Universal Instruments Corporation as a Vice Preseidnet of a new division to focus on Flip Chip asembly machines. Afterwards, he left for Europe as the Die Bonder Vice Presient of Kulicke and Soffa and General manager of Alphasem and then as CEO of ALSI who design Laser Dicing and Grooving machines that was rhen sold to ASM Pacific Technology.His present positio is President of ASM NEXX who design and build Wafer and Panel Plating Tools

Richard Boulanger
President

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ICM
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