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Recent advancements in tailor-made silicon substrate manufacturing

NOV
12
2019
12. NOV 2019

Presentation Halle ICM - Internationales Congress Center München SEMICON EUROPA > Strategic Materials Conference > Session 2 - Substrates

17:10-17:35 Uhr | ICM - Internationales Congress Center München ICM Room 13a, 1st Floor

Themen: SEMICON EUROPA

Chairman: Douglas Guerrero (, Brewer Science)

Format: Presentation

Sprache: Englisch

There is a constant drive towards increased reliability, quality, and performance of silicon-based devices. To respond to this demand, we present the manufacturing process platform for value-added Si substrates with fully customized material properties and design, including embedded patterns and SOI layers with high layer thickness precision. These wafers, acting as a partially built component, not only enhance the profitability of user’s further processing but also improve the long-term reliability due to the state-of-the art fusion bonding quality.We demonstrate the achievements in recently started industrial scale manufacturing. The fully in-house solution, designed to fit for volume production, combines the expertise in bonded-SOI processing with patterning and DRIE etching technologies. Thanks to our own crystal growth capability, the starting silicon properties such as orientation, resistivity and dopants can be freely adjusted. As a further advantage, integrated process scheduling enables reasonable cycle times as the approach decreases handling and transportations between foundries and critical process steps.A special attention has been paid to end user’s quality requirements in tool and process selection, as well as in associated measurements, inspections and control. The defectivity of the embedded patterned surface is compared between in-house and service-contractor manufacturing, showing clear improvement with the substrate-integrated process done in-house.The substrate tailoring has potential in various MEMS, sensor and photonics applications requiring buried cavities, poly-Si filled TSV structures, or patterned multi-layer SOI design.

Informationen

Dr. Päivi Sievilä

Dr. Päivi Sievilä is a professional in the field of silicon and SOI wafers with extensive experience in research, industrial process engineering and development. Currently she works as Customer Support Engineer in Okmetic’s global technical customer support. Her field of responsibility covers collaboration with European customers. She received her PhD from the Department of Micro- and Nanosciences, Aalto University in 2013. Her thesis focused on microfabrication technologies for silicon-based sensors.

Dr. Päivi Sievilä
Customer Support Engineer

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