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Addressing Impact of Shrinking Line/Space Dimensions on PR Strip, UBM/RDL Etch and Wafer Thinning Processes

NOV
13
2019
13. NOV 2019

Presentation Halle ICM - Internationales Congress Center München SEMICON EUROPA > Advanced Packaging Conference > Session 4: New Materials and Processing in Packaging

10:30-10:55 Uhr | ICM - Internationales Congress Center München ICM Room 13b, 1st Floor

Themen: SEMICON EUROPA

Chairman: Jens Mueller (, Test)

Format: Presentation

Sprache: Englisch

Moore’s law sharpened focus on shrinking gate dimensions to drive performance and cost. This paper explains emerging challenges as Moore’s law slows, with focus transitioning to the packaging side as the industry adopts heterogeneous integration and smaller line/space dimensions for better performance.Technical requirements are more challenging; e.g., the interconnect and bumping process flow is as follows: barrier/seed layer deposition, patterning, plating, photoresist (PR) strip, and etch. Designers are using redistribution layers (RDL) in flip-chip designs to redistribute I/O pads to bump pads without changing the I/O pad placement. Under bump metallization (UBM) enhances reliability by providing the critical interface between the metal pad and solder bump. Higher I/O density with improved reliability and performance also leads to shrinking line geometries (from >10µm to sub-1µm) along with smaller bump diameter and pitch. As a result, the photoresist becomes more difficult to remove, calling for more effective methods.Shrinking dimensions pose similar challenges in UBM/RDL etch. A critical requirement is to minimize undercut while removing barrier/seed layers. Higher undercut impacts mechanical integrity while insufficient removal leads to poor yield.As thinner devices also drive performance and/or optimized form factor, wafers get thinner in MEMS, Power, RF, Image Sensors. Grinding damages the wafer surface, leaving microcracks, residual stresses and edge chipping. A subsequent process is needed to repair the surface, reduce stress and achieve desired thickness. Wet processing has emerged as a preferred method for surface treatment and wafer thinning while offering higher uniformity at lower cost.This presentation explains technical results for PR strip, UBM/RDL etch and wafer thinning steps.

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Author,
Veeco

Anil Vijayendran

Anil Vijayendran earned his MBA from the University of California, Berkeley, and a master’s and bachelor’s degree in chemical engineering from Massachusetts Institute of Technology. He has served in roles of increasing responsibility in technical, marketing and product development and is currently vice president of marketing of Veeco’s precision surface processing business unit, where he leads all end-to-end product management and marketing for the PSP division. Prior to his role with Veeco, Vijayendran was the vice president of technical marketing for MiaSolé and has previously served as the director of product management at Novellus Systems, a Lam Research company.

Anil Vijayendran

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