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Effect of harsh temperature ramp rates on solder joints of Wafer-Level CSPs in board level reliability tests.

NOV
12
2019
12. NOV 2019

Presentation Halle ICM - Internationales Congress Center München SEMICON EUROPA > Advanced Packaging Conference > Session 3: Test and Reliability II

16:55-17:20 Uhr | ICM - Internationales Congress Center München ICM Room 13b, 1st Floor

Themen: SEMICON EUROPA

Chairman: Klaus Pressel (, Infineon)

Format: Presentation

Sprache: Englisch

Board level reliability qualifications based on automotive mission profiles take a huge amount of time. This is caused by harsh operation conditions in the field as well as the extended lifetime requirements compared to consumer electronics. Further reduction of the testing time is the major goal of accelerated testing. Temperature cycling tests simulate thermomechanical stress in the component and its interconnect technology. Optimizing the parameters of thermal cycling conditions is the most used approach in the literature to accelerate field relevant failure mechanism. A decrease in the parameter temperature ramp time influences testing time in two ways: Reduction in cycles to failure and direct reduction of cycle time. However, the quantitative effect on lifetime and the resulting failure mechanism have to be evaluated, especially for conditions which are less usual like liquid to liquid thermal shock. Some authors argue, that different failure mechanism may be triggered by those potentially exaggerated conditions. Nevertheless, cross sections of liquid to liquid aged components can only rarely be found in the literature. This investigation shows the lifetime as well as the failure mechanism in a Wafer-Level CSP and a common 1206 resistor over a broad range of different ramp rates. This includes conventional thermal cycling and thermal shock up to liquid to liquid testing. Electrical monitoring of the WLCSP solder joints indicates, that the characteristic lifetime is decreased for harsh ramp rates. Cross sections demonstrate, that the failure mechanism is solder fatigue in all cases. Detailed analysis shows, that the microstructure aging is comparable in all stages of damage evolution in terms of precipitate coarsening, onset of recrystallization and crack growth.

Informationen

Author,
BMW Group

Simon Schambeck

Simon Schambeck received his Bachelor’s degree in Physics at the University of Regensburg, Germany in 2014 and finished his Master’s Degree in Physics in 2017. He wrote his Master’s Thesis in a working group focusing on epitaxial nanostructures. Parallel to his studies he assisted in development departments at OSRAM OLED GmbH and BMW Group. Currently he is working in the engineering department for semiconductor standards and environment simulation of the BMW Group in Munich. He is doing research on board level reliability testing for his PhD thesis including simulation of solder joint lifetime, test definition and characterization of failure mechanisms.

Simon Schambeck

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