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Chip Package Interaction Test structure design to address challenges from products with RF specific back end of line metallization options on Flip Chip ETS substrate

NOV
12
2019
12. NOV 2019

Presentation Halle ICM - Internationales Congress Center München SEMICON EUROPA > Advanced Packaging Conference > Session 3: Test and Reliability II

16:30-16:55 Uhr | ICM - Internationales Congress Center München ICM Room 13b, 1st Floor

Themen: SEMICON EUROPA

Chairman: Klaus Pressel (, Infineon)

Format: Presentation

Sprache: Englisch

The growing interest in applications for 5G communication has generated some efforts in developing new Back End of Line (BeoL) schemes in the Semiconductors industry. In particular, BeoL stacks with Ultra Thick Metal (UTM) for RF mmWAVE applications have come to the forefront. However the high thickness of the UTM (~3um) can induce significant residual stress, which brings up new challenges related to wafer and die warpage. The die warpage becomes quite critical during the temperature cycle that the silicon die undergoes during the flip chip assembly process.In addition, the market pressure to reduce assembly costs in packaging is driving the use of coreless Embedded Trace Substrates (ETS). The use of low cost substrates such as ETS can potentially reduce the assembly process margins: an ETS coreless substrate can be more prone to warpage during the assembly process than core substrates. The combination of silicon die and ETS substrate warpage can cause assembly yield loss as well as potential reliability issues.In this work we present the study of a Chip Package Interaction (CPI) test vehicle, with a Cu double Ultra Thick Metal implemented in a GLOBALFOUBDRIES 22FDX BeoL stack. This test vehicle has been assembled using an Embedded Trace Substrate (ETS). This work is focusing on testing CPI structures that have been implemented to catch warpage and stress related fails through electrical test before and after the reliability environmental stress. Three different types of CPI sensor structures have been designed and implemented in the CPI test vehicle, in order to detect cracks in the BeoL and die warpage driven fails during and post assembly.Assembled dies of this test vehicle have undergone JEDEC standard reliability environmental test stresses. In conclusion, the GLOBALFOUNDRIES 22FDX double UTM BeoL used in this work proved to be robust enough to pass the JEDEC standard reliability environmental test stress in a standard flip chip package with ETS substrate.

Informationen

Author,
Globalfoundries

Simone Capecchi

Simone CapecchiMember of Technical Staff, Reliability EngineeringGlobalfoundries, Dresden, GermanySimone Capecchi is currently employed as Member of Technical Staff in the Reliability Engineering Group of Globalfoundries in Dresden, Germany. The focus of his work is on Chip Package Interaction Reliability.Still in Globalfoundries Dresden, Simone spent four years in the wafer bumping engineering group sustaining high volume production as well as introducing new technologiesPrior to joining Globalfoundries, Simone lead an engineering group in STMicroelectronics for 3 years.Simone also worked as Senior Engineer in Intel Ireland and Intel US, sustaining high volume production as well transferring technologies from the development site to a high volume manufacturing site.Simone has also experience in the optical components fabrication in Nortel Networks where he developed processes for telecommunication components.

Simone Capecchi
MTS Reliability Engineer

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