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Enablement of Energy-efficient Machine Learning hardware through System-Technology Co-optimization

NOV
13
2019
13. NOV 2019

Presentation Halle B1 SEMICON EUROPA > TechARENA 1 & 2 - Technological Platform for Innovation > Disruptive Computing

13:25-13:45 Uhr | Halle B1 Tech Arena 2, Booth B1.770

Themen: SEMICON EUROPA

Format: Presentation

Sprache: Englisch

The demand for deep learning and statistical inference is driving the hardware industry towards Machine Learning (ML)-specialized hardware. Conventional solutions for efficient computation of ML-based tasks are based on GPU architectures possibly with specialization for ML, heterogeneous system level integration with CPU and FPGA, and full ASIC implementations. We propose system-technology co-optimization: the co-optimization of algorithm, architecture, circuit and novel devices in a single framework to develop optimized technology for Machine Learning.Energy-efficiency of ML hardware implementations is a key target. In many embedded applications it is not possible, due to energy and latency constraints, to use cloud-based ML implementations. Data analysis at the source of the data, provides the opportunity to embed intelligence in the devices, avoiding the need to send raw data to the cloud for analysis, and in this way obtain vastly more energy efficient and low latency solutions for truly smart devices.In this presentation, we will discuss the following topics:Novel technology solutions (memory and logic devices) that are optimized for executing ML inference algorithm in the hardware.Co-optimization of ML algorithm and system architecture to reduce the memory bottleneck and power consumption, allow for a minimization of required memory space and minimize the occupied silicon area (i.e. chip cost) while maintaining target accuracy, latency and throughput.Development of prototype silicon to showcase the capability of the proposed approaches on industry-standard benchmarks for Machine Learning.

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Author,
imec

Arindam Mallik

Arindam Mallik is Machine Learning Program Manager at imec.He received his M.S, and PhD degree in Electrical Engineering and Computer Science from Northwestern University, USA in 2004 and 2008, respectively. Arindam is a technologist working on Design Technology Co-Optimization techniques for the past 15 years. He currently manages imec’s Machine Learning Program, focusing on technology innovation needed for optimum performance of Machine Learning/Artificial Intelligence platforms. His research interests include system/design-technology co-optimization, economics of semiconductor manufacturing, and system-level analysis of advanced technology nodes. He has authored or co-authored more than 100 papers in international journals, conference proceedings, and holds number of international patent families.

Arindam Mallik
Program Manager

Lageplan

Eingang
Nord-West
ICM
Eingang
Nord
Eingang
West
Atrium
Eingang
Nord-Ost
Eingang
Ost
Conference
Center Nord
Freigelände
C1
C2
C3
C4
C5
C6
B0
B1
B2
B3
B4
B5
B6
A1
A2
A3
A4
A5
A6

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